The next transistor: planar, fins, and SOI at 22 nm
The race is on to redefine the transistor. Processdevelopers working on 22-/20-nm logic processes appear to be scrambling tointroduce new kinds of transistors for this node. Intel has made a huge fanfareover their tri-gate device. Many researchers are pushing finFETs. A powerfulgroup of mainly European organizations, including ARM and US-based Globalfoundries,is serious about fully-depleted SOI (fdSOI.) And recently, start-up Suvolta andFujitsu described yet another alternative.
All this might appear fascinating for device designers, andirrelevant to chip designers. But decisions on transistor design will haveprofound downstream impacts-from the craft of cell design to the work ofphysical-design teams, and even to the logic designer's struggles with powerand timing closure.
What'sthe problem?
Why are process engineers so determined to upset the applecart? The short answer is short-channel effects. Pursuit of Moore's Law hascontinually shrunk the channel length of the MOSFET. This contraction improves transistor density and, other factor fixed, switching speed. The problem isthat shortening the channel plays havoc with those other factors-about a dozendifferent havocs, actually, that get lumped under the label of short-channeleffect. Most of these we can summarize by a generalization: as the drain getscloser to the source, it gets harder and harder for the gate to pinch off thechannel current (figure 1, below). The result is sub-threshold leakage current.
This battle against leakage current has been going on sinceat least the 90-nm node. The point of the whole high-k/metal-gate (HKMG)transition was to give the gate more control over the channel current withoutletting gate leakage get out of control. But by the 22-nm node, many arearguing, the planar MOSFET will have lost that war. There will be no way todeliver adequate leakage control at adequate performance. "With HKMG weaddressed gate leakage," one expert said. "Now we have to address channelleakage."
Planarone more time?
Not everyone agrees that the planar MOSFET is history. Principalamong the dissenters is TSMC, which stated in February that it would use planartransistors in its 20-nm foundry process. There are strong arguments for thisposition, also held-with one major caveat-by Globalfoundries. Designers arefamiliar with short-channel planar MSOFETs, for all their shortcomings. Thisshould make rescaling of cell libraries and hard IP blocks relativelystraightforward. Leakage and threshold variations may be worse than at 28 nm,but the design community has tools, including aggressive power management,variation-tolerant circuits, and statistical timing analysis, to cope withthese problems. And when all the issues are on the table, a foundry must dowhat its lead customers-FPGA vendors, networking IC giants, and to some extentARM-ask of it.
Still, there is much skepticism. "TSMC stated that theywould use a replacement-metal-gate planar process at 20 nm," observed NovellusVice President Girish Dixit, "but that determination may have changed. HKMG cancontrol leakage, but a planar transistor will still have inferior I-on/I-offcharacteristics." If TSMC's early adopters find themselves at a competitivedisadvantage because of the planar transistor, they may force the giant into afinFET half-node. The confrontation would most likely arise in the mobilemarket, where ARM's fabless silicon partners will face competition from Intel'sAtom processor, newly rejuvenated by that company's 22-nm tri-gate process.
Therise of the fin
The next-transistor debate matriculated from a decade in thecloistered but technically accurate halls of process engineering conferences tothe public forum with Intel's May announcement of their 22-nm so-calledtri-gate process. The roll-out, probably intended to counter ARM's growingmomentum in the mobile space rather than to advance the discussion in circuit design,significantly reduced the signal-to-noise level about new transistortechnology.
Intel's tri-gate device is a finFET, pure and simple.Industry experts dismiss Intel's attempts to claim a significant difference. Assuch, it is one instance of a decade-old, industry-wide attack on short-channeleffect-an effort that began at industry consortium IMEC at about the same timeas it did at Intel. "Everyone in the industry has been developing finFETtechnology," one process expert said. "The difference is in what they havechosen to announce."
All finFET programs-indeed, all the approaches tonext-transistors-rest on a single concept: the fully-depleted channel. Loosely,the concept is to give the gate so much control over the electric field in thechannel that the gate can deplete the channel of carriers entirely. This ofcourse eliminates the dominant conduction mechanism in the channel, and ineffect turns the transistor off.
But how to do that? In a planar device, the depth of thechannel and effects from the junction formed between the drain and the siliconaround it alter the electric field in the channel and interfere with depletion.Somehow you have to make the channel thin enough and far enough from the drainjunction to permit the gate to fully deplete the conduction region.
The finFET gives circuit designers a V-I curve they've onlybeen able to dream about since 130 nm. But it also brings issues. One is simplybuilding the devices. "Making the fins, and preserving them through subsequentprocessing steps, are hard tasks," warned Applied Materials Silicon SystemsGroup Vice President and CTO Klaus Schuegraf. "You must etch over the edges oftall structures, uniformly dope complex 3D surfaces, and lay down all thedifferent films in the gate stack so that they conform exactly to the surfaceof the fin. These requirements bring about many changes in materials, and somechanges in equipment. The number of mask layers won't change much, but thenumber of processing steps will certainly go up."
Continue reading: Fins and the rest of us
The next transistor: planar, fins, and SOI at 22 nm
All this might appear fascinating for device designers, andirrelevant to chip designers. But decisions on transistor design will haveprofound downstream impacts-from the craft of cell design to the work ofphysical-design teams, and even to the logic designer's struggles with powerand timing closure.
What'sthe problem?
Why are process engineers so determined to upset the applecart? The short answer is short-channel effects. Pursuit of Moore's Law hascontinually shrunk the channel length of the MOSFET. This contraction improves transistor density and, other factor fixed, switching speed. The problem isthat shortening the channel plays havoc with those other factors-about a dozendifferent havocs, actually, that get lumped under the label of short-channeleffect. Most of these we can summarize by a generalization: as the drain getscloser to the source, it gets harder and harder for the gate to pinch off thechannel current (figure 1, below). The result is sub-threshold leakage current.
Figure 1: As channel length shrinks, the electrical characteristics of the channel go wrong.
This battle against leakage current has been going on sinceat least the 90-nm node. The point of the whole high-k/metal-gate (HKMG)transition was to give the gate more control over the channel current withoutletting gate leakage get out of control. But by the 22-nm node, many arearguing, the planar MOSFET will have lost that war. There will be no way todeliver adequate leakage control at adequate performance. "With HKMG weaddressed gate leakage," one expert said. "Now we have to address channelleakage."
Planarone more time?
Not everyone agrees that the planar MOSFET is history. Principalamong the dissenters is TSMC, which stated in February that it would use planartransistors in its 20-nm foundry process. There are strong arguments for thisposition, also held-with one major caveat-by Globalfoundries. Designers arefamiliar with short-channel planar MSOFETs, for all their shortcomings. Thisshould make rescaling of cell libraries and hard IP blocks relativelystraightforward. Leakage and threshold variations may be worse than at 28 nm,but the design community has tools, including aggressive power management,variation-tolerant circuits, and statistical timing analysis, to cope withthese problems. And when all the issues are on the table, a foundry must dowhat its lead customers-FPGA vendors, networking IC giants, and to some extentARM-ask of it.
Still, there is much skepticism. "TSMC stated that theywould use a replacement-metal-gate planar process at 20 nm," observed NovellusVice President Girish Dixit, "but that determination may have changed. HKMG cancontrol leakage, but a planar transistor will still have inferior I-on/I-offcharacteristics." If TSMC's early adopters find themselves at a competitivedisadvantage because of the planar transistor, they may force the giant into afinFET half-node. The confrontation would most likely arise in the mobilemarket, where ARM's fabless silicon partners will face competition from Intel'sAtom processor, newly rejuvenated by that company's 22-nm tri-gate process.
Therise of the fin
The next-transistor debate matriculated from a decade in thecloistered but technically accurate halls of process engineering conferences tothe public forum with Intel's May announcement of their 22-nm so-calledtri-gate process. The roll-out, probably intended to counter ARM's growingmomentum in the mobile space rather than to advance the discussion in circuit design,significantly reduced the signal-to-noise level about new transistortechnology.
Intel's tri-gate device is a finFET, pure and simple.Industry experts dismiss Intel's attempts to claim a significant difference. Assuch, it is one instance of a decade-old, industry-wide attack on short-channeleffect-an effort that began at industry consortium IMEC at about the same timeas it did at Intel. "Everyone in the industry has been developing finFETtechnology," one process expert said. "The difference is in what they havechosen to announce."
All finFET programs-indeed, all the approaches tonext-transistors-rest on a single concept: the fully-depleted channel. Loosely,the concept is to give the gate so much control over the electric field in thechannel that the gate can deplete the channel of carriers entirely. This ofcourse eliminates the dominant conduction mechanism in the channel, and ineffect turns the transistor off.
But how to do that? In a planar device, the depth of thechannel and effects from the junction formed between the drain and the siliconaround it alter the electric field in the channel and interfere with depletion.Somehow you have to make the channel thin enough and far enough from the drainjunction to permit the gate to fully deplete the conduction region.
Figure 2: Fins can be incredibly small and delicate, but details of shape and aspect ratio determine transistor characteristics.The finFET solution is to stand the channel on its edge,above your choice of either the silicon surface or an insulating oxide layer,and to drape the HKMG gate stack over the resulting fin like a wet blanket.This fin-shaped channel is very thin (figure 2, right) and working from three sides,the gate can successfully create a depletion region that blocks the channelentirely.
The finFET gives circuit designers a V-I curve they've onlybeen able to dream about since 130 nm. But it also brings issues. One is simplybuilding the devices. "Making the fins, and preserving them through subsequentprocessing steps, are hard tasks," warned Applied Materials Silicon SystemsGroup Vice President and CTO Klaus Schuegraf. "You must etch over the edges oftall structures, uniformly dope complex 3D surfaces, and lay down all thedifferent films in the gate stack so that they conform exactly to the surfaceof the fin. These requirements bring about many changes in materials, and somechanges in equipment. The number of mask layers won't change much, but thenumber of processing steps will certainly go up."
Continue reading: Fins and the rest of us
The next transistor: planar, fins, and SOI at 22 nm
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