FPGA / PLD Lattice targets changing interfaces with tiny FPGA

FPGA / PLD Lattice targets changing interfaces with tiny FPGA

2013/09/24

Lattice Semiconductor’s latest MachXO3 FPGA is designed as a small package, low cost device offering interfaces using both parallel and serial I/O.

According to Brent Przybus, director, product and corporate marketing at Lattice: “As system performance and complexity increases, I/O interfaces often become the bottleneck. Designers want to use the most advanced components, but have to deal with any number of interface standards, many of which are still evolving or are new to many designers, such as MIPI.”

The 640-to-22K logic-cell family is available in a 2.5×2.5mm wafer-level chip-scale packaging.

There are also 540 I/O count devices, as well as devices with 3.125Gbit/s SERDES capabilities.

First production MachXO3 device shipments scheduled for the end of 2013 and pricing starting below $1.00 in high volume.

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